Welcome to the website of the Asynchronous Circuit and System
Design Group of the CARV laboratory of FORTH-ICS!
The goal of our group is to perform world-class research into
the field of Asynchronous
Circuit and System Design and promote the industrial
take-up of asynchronous design.
Our research ranges from transistor level modelling and
understanding of asynchronous circuit phenomena to asynchronous
design techniques and EDA tools for asynchronous design.
Asynchronous Design
Asynchronous design is not new. Asynchronous design methods
date back to the 1950's. However, the clock signal, which is
traditionally used by circuit designers, in order to enforce
global timing to a digital circuit, has historically been
considered as an essential
device.
The following is a famous quote by Turing, who consided the
clock signal as necessary for the operation of a digital
computer and claimed that asynchronous circuits are hard to
design:
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"We might say that the
clock enables us to introduce a discreteness into time,
so that time for some purposes can be regarded as a
succession of instants instead of a continuous flow. A
digital machine must essentially deal with discrete
objects, and in the case of ACE this is made possible by
the use of the clock. All other computing machines except
for human and other brains that I know of do the same.
One can think up ways of avoiding it, but they are very
awkward..."
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Alan Turing, 1912-1954
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More than 60 years later, asynchronous design has experienced
important breakthroughs both in design methods and approaches
and practical demonstrator designs from both academia and
industry.
Advantages of Asynchronous Design
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Elimination of clock tree
related problems (clock skew and clock power): as
digital systems become larger, an increasing amount of effort
is required to enforce the global timing model, with
significant effort being paid to guarantee clock skew and
even clock power are kept under control. In asynchronous
systems, skew can be tolerated and power is well controlled.
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Average-case
performance: in synchronous design, cycle time and
performance are dictated by worst-case conditions, as clock
period is set to be long enough to accomodate the slowest
possible data propagation. Asynchronous circuits can change
their speed dynamically and their performance is data-driven
and governed by average-case delay.
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Adaptability to processing
and environmental variations: the delay of a VLSI
circuit varies significantly over processing runs, supply
voltages and operating conditions. Synchronous circuit have a
fixed clock rate set according to some allowed degree of
variations. Asynchronous circuits are adaptive and can
operate correctly under all variations with their speed
increasing or descreasing, as is necessary.
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Modularity and
re-use: asynchronous components have plug-and-play
capabilities because of the absence of global timing
assumptions.
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Lower power and lower
Electromagnetic Emissions: asynchronous circuits
reduce synchronisation power and automatically
power-down unused components; asynchronous circuits are also
quiet as they avoid unneeded signal transitions and spread
out needed signal transitions.
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