ASYNC 2004  - Tutorials

This year, the ASYNC conference is offering three excellent hands-on tutorials on asynchronous design flows.

We encourage you to register early for the tutorials !


Tutorial Day - Monday 19th of April 2004

The ASYNC 2004 symposium will be preceded by hands-on tutorials featuring three complete CAD flows for asynchronous design on April 19th 2004: the Caltech design methodology, the Phased Logic tool from Mississipi State University, and the Cash Flow tool from Carnegie Mellon Univesity. The tools will be installed on a PC server, and the participants will be guided through a series of hands-on exercises employing each one of the tools.


Coach services have been arranged from Knossos Royal Village Hotel to FORTH and back.

ASYNC 2004 Tutorial Day Programme

08:30 Departure of ASYNC Tutorial Coach from Knossos Royal Village to FORTH.

09:30-11:00 Tutorials 1 and 2.A. (first part)

11:00-11:30 Coffee Break

11:30-13:00 Tutorials 1 and 2.A. (second part)

13:00-14:30 Lunch

14:30 First Departure of ASYNC Tutorial Coach from FORTH to Knossos Royal Village.

14:30-15:00 Tutorials 1 and Tutorial 2.B. (third part)

15:00-15:30 Coffee Break

15:30-17:00 Tutorials 1 and Tutorial 2.B. (fourth part)

17:00 End of Tutorial Day

17:15 Second Departure of ASYNC Tutorial Coach from FORTH to Knossos Royal

ASYNC 2004 Tutorials

1. Full-Day Tutorial - Caltech Asynchronous Synthesis Tools (CAST)

This tutorial will present the methods and CAD tools developed at Caltech for the design of high-performance asynchronous VLSI systems. This tutorial will occupy most of the day. The first half of the tutorial will be a presentation of the design method. We will describe the different representation languages: CHP, cast, hse, prs, m33 and we will show how to synthesize a circuit from a high-level description down to layout. In the first example, the different synthesis algorithms will be applied by hand.

In the second part of the tutorial, we will use a larger example (the fetch unit of the Lutonium microcontroller) to present the more advanced aspects of the method and to introduce the tools (high-level synthesis, simulation, cosimulation, and physical design). The attendees will be asked to design one chosen unit of the Fetch.

A good general knowledge of asynchronous design is preferred but not required. A general knowledge of CMOS technology and VLSI is expected.

2.A. Half-Day Tutorial (morning) - Translating C programs into pipelined asynchronous circuits with CASH

In this tutorial we present a compilation framework for automatically translating ANSI C programs into pipelined asynchronous circuits. The framework is embodied in the CASH compiler, a Compiler for Application-Specific Hardware. CASH generates dataflow machines implemented as asynchronous circuits that directly implement the source program, without using any interpretative structures.  This tutorial is composed of three parts.

The first part describes the compilation methodology and internal representation of CASH. The second part describes CAB, the CASH Asynchronous Back-end, which translates the Pegasus intermediate representation into asynchronous circuits.

The third part of the tutorial is a hands-on demonstration of the capabilities of CASH. Attendees are shown how to carry selected C kernels through all compilation steps, and how compilation options influence the output. Attendees will also compile and simulate their own C implementation of a DSP application.

2.B. Half-Day Tutorial (afternoon) - Phased Logic: An Automated Clocked to Clockless Methodology

This tutorial is devoted to the coarse-grain PL methodology.

Attendees will produce working PL designs implemented as gate level Verilog netlists back-annotated with pre-layout SDF timing information. The starting point for a coarse-grain PL design is clocked RTL, where the top level RTL partitioning determines the individual blocks in the final PL implementation. The mapping process is automated once the clocked netlist has been synthesized.

The designer must identify early evaluation opportunities, and a simple configuration file is used to provide this information to the PL mapping tools. A separate PL timing analysis tool can be used to estimate system performance before Verilog gate level simulation, and provide hints as to where slack-matching buffers should be inserted to improve performance.

ASYNC 2004 Tutorial Pre-Registration

You can register for the ASYNC 2004 Tutorials on Monday 19th of April at 09:15 in the morning at FORTH-ICS, however it is preferable that tutorial attendees pre-register by sending an email to the ASYNC 2004 Secretary, Mrs. Maria Prevelianaki,, stating your name and the tutorial that you are willing to attend.